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Freescale Semiconductor Advance Information
Document Number: MC33996 Rev. 8.0, 8/2008
16 Output Switch with SPI Control
The 33996 is a 16-output low side switch with a 24-bit serial input control. It is designed for a variety of applications including inductive, incandescent, and LED loads. The Serial Peripheral Interface (SPI) provides both input control and diagnostic readout. A Pulse Width Modulation (PWM) control input is provided for pulse width modulation of multiple outputs at the same duty cycle. A dedicated reset input provides the ability to clear all internal registers and turn all outputs off. The 33996 directly interfaces with micro controllers and is compatible with both 3.3 and 5.0V CMOS logic levels. The 33996, in effect, serves as a bus expander and buffer with fault management features that reduce the MCU's fault management burden. Features * Designed to operate 5.0V < VPWR < 27V * 24 Bit SPI for control and fault reporting, 3.3/5.0V compatible * Outputs are current limited (0.9 to 2.5A) to drive incandescent lamps * Output voltage clamp of +50V during inductive switching * On/Off control of open load detect current (LED application) * VPWR standby current < 10A * RDS(ON) of 0.55 at 25C typical * Independent over-temperature protection * Output selectable for PWM control * Output ON short-to-VBAT and off short-to-ground /open detection * Pb-free packaging designated by suffix code EK
33996
LOW SIDE SWITCH
EK SUFFIX (PB-FREE) 98ARL10543D 32-PIN SOICW EXPOSED PAD
ORDERING INFORMATION
Device MC33996EK/R2 MCZ33996EK/R2 Temperature Range (TA) -40C to 125C Package 32 SOICW-EP
Vdd 3.3 V/5.0 V
VPWR
VBAT
33996
SOPWR SCLK CS SI SO PWM RST VPWR OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 OUT15 GND
VDD MCU SCLK CS MISO MOSI PWM RST
Solenoid/Relay
LED
/8
Lamp
Figure 1. 33996 Simplified Application Diagram
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2007-2008. All rights reserved.
IINTERNAL BLOCK DIAGRAM
IINTERNAL BLOCK DIAGRAM
VPWR OUT0 VDD Over-voltage Detect OVD VDD RB SFPDB SFL CS SCLK SI SO CSI CSBI Voltage Regulator GE OT SF OF VDD Bias Gate Control 50V
PWM 10A RST CS SCLK SI 10 A SO SOPWR Serial D/O Line Driver 25A 10A Input Buffers 10A
To Gates 1 to 15
OUT1-15
Open Load Detect Enable
VRef
ILimit 50A Short and Open Load Detect Over-temperature Detect From Detectors 1 to 15 RS
SPI Interface Logic
GND (8)
Figure 2. 33996 Simplified Internal Block Diagram
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Analog Integrated Circuit Device Data Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
OUT0 OUT1 SOPWR OUT2 OUT3 VPWR GND GND GND GND SCLK OUT4 OUT5
CS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OUT15 OUT14 PWM OUT13 OUT12
RST
OUT6 OUT7
GND GND GND GND SO OUT11 OUT10 SI OUT9 OUT8
Figure 3. 33996 Pin Locations Table 1. Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 10.
Pin 1, 2, 4, 5, 12, 13, 15 - 18, 20, 21, 28, 29, 31, 32 3 6 7- 10, 23 - 26 11 14 19 22 27 30 33 Pin Name OUT0 - OUT15 Formal Name Output 0 - Output 15 Open drain output pin. Definition
SOPWR VPWR GND SCLK CS SI SO RST PWM EP
SOPWR Supply Battery Input Ground System Clock Chip Select Serial Input Serial Output Reset PWM Control Exposed Pad
Power supply pin to the SO output driver. Battery supply input pin. Ground for logic, analog, and power output devices. System Clock for internal shift registers of the 33996. SPI control chip select input pin from the MCU to the 33996. Serial data input pin to the 33996. Serial data output pin. Active low reset input pin. PWM control input pin. Supports PWM on any combination of outputs. Device will perform as specified with the Exposed Pad un-terminated (floating) however, it is recommended that the Exposed Pad be terminated to system ground.
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted.
Rating ELECTRICAL RATINGS VPWR Supply Voltage (1) SO Output Driver Power Supply Voltage (1) SPI Interface Logic Input Voltage (CS, PWM, SI, SO, SCLK, RST) Output Drain Voltage Frequency of SPI Operation Output Clamp Energy (3) ESD Voltage
(4) (2) (1)
Symbol
Value
Unit
VPWR SOPWR VIN VD
-1.5 to 50 -0.3 to 7.0 -0.3 to 7.0 -0.3 to 45 6.0 50
V V V V MHz mJ V
fSPI
ECLAMP
Human Body Model Machine Model THERMAL RATINGS Operating Temperature Ambient Junction Case Storage Temperature Power Dissipation (TA = 25C)
(5)
VESD1 VESD2
2000 200
C
TA TJ TC TSTG PD TPPRT RJA RJL RJC -40 to 125 -40 to 150 -40 to 125 -55 to 150 1.7 Note 7
C
W C C/W
Peak Package Reflow Temperature During Reflow (6), (7) Thermal Resistance Junction-to-Ambient Junction- to-Lead (9) Junction-to-Flag Notes 1. 2. 3. 4. 5. 6. 7.
(8)
75 8.0 1.2
Exceeding these limits may cause malfunction or permanent damage to the device. This parameter is guaranteed by design but not production tested. Maximum output clamp energy capability at 150C junction temperature using single nonrepetitive pulse method. ESD data available upon request. ESD testing is performed in accordance with the Human Body Model (CZAP = 100pF, RZAP = 1500) and the Machine Model (CZAP = 200pF, RZAP = 0). Maximum power dissipation with no heat sink used. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. Tested per JEDEC test JESD52-2 (single-layer PWB). Tested per JEDEC test JESD51-8 (two-layer PWB).
8. 9.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 3.1V SOPWR 5.5V, 5.0V VPWR 18V, -40C TA 125C unless otherwise noted. Where applicable, typical values noted reflect the parameter `s approximate value with VPWR = 13V, TA = 25C.
Characteristic POWER SUPPLY (VPWR) Supply Voltage Range Fully Operational Supply Current All Outputs ON, IOUT = 0.3A Sleep State Supply Current at RST 0.8 and/or SOPWR 1.5V Over-voltage Shutdown Over-voltage Shutdown Hysteresis VPWR Under-voltage Shutdown SPI Interface Logic Supply Voltage SPI Interface Logic Supply Current (RST Pin High) SPI Interface Logic Supply Current (RST Pin Low) SPI Interface Logic Supply Under-voltage Lockout Threshold POWER OUTPUT (VPWR) Drain-to-Source ON Resistance (IOUT = 0.35A, VPWR = 13V) TJ = 125C TJ = 25C TJ = -40C Output Self-Limiting Current Outputs Programmed ON Output Fault Detect Threshold (10) Outputs Programmed OFF Output Off Open Load Detect Current (11) Outputs Programmed OFF (VPWR = 5.0V, 13V, 18V) Output Clamp Voltage IOUT = 20mA Output Leakage Current SOPWR 1.5V, VOUT 1-16 = 18V Over-temperature Shutdown (Outputs OFF) (12) Over-temperature Shutdown Hysteresis (12) TLIM TLIM (hys) IOUT(lkg) -10 155 5.0 2.0 165 10 10 180 20 C C VCL 45 50 55 A I OCO 25 50 100 V VOUTth (F) 2.5 3.0 3.5 A I OUT (lim) 0.9 1.2 2.5 V A RDS(ON) - - - 0.75 0.55 0.45 1.1 - - VPWR (FO) IPWR (ON) IPWR (SS) VOV VOV (HYS) VPWR (UV) SOPWR ISOPWR(RSTH) ISOPWR(RSTL) SOPWR (UNVOL) 5.0 - _ 27.5 0.6 - 3.1 100 -10 1.5 - 4.0 1.0 31.5 1.4 3.2 - - - 2.5 27 8.0 10 35 2.3 4.0 5.5 500 10 3.0 V mA A V V V V A A V Symbol Min Typ Max Unit
Notes 10. Output Fault Detect Thresholds with outputs programmed OFF. Output Fault Detect Thresholds are the same for output open and shorts. 11. Output OFF Open Load Detect Current is the current required to flow through the load for the purpose of detecting the existence of an open load condition when the specific output is commanded to be OFF. 12. This parameter is guaranteed by design; however, it is not production tested.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 3.1V SOPWR 5.5V, 5.0V VPWR 18V, -40C TA 125C unless otherwise noted. Where applicable, typical values noted reflect the parameter `s approximate value with VPWR = 13V, TA = 25C.
Characteristic DIGITAL INTERFACE (RST, SI, CS, SCLK, SO, PWM) Input Logic Voltage Thresholds (13) Input Logic Voltage Thresholds for RST SI Pull-down Current SI = 5.0 V
CS Pull-up Current CS = 0 V
Symbol
Min
Typ
Max
Unit
VINLOGIC VINRST I SI
0.8 0.8
- -
2.2 2.2
V V A
2.0 I CS -30 I SCLK 2.0 I RST 5.0 I PWM VSOH SOPWR - 0.4 VSOL - CIN - 2.0
10
30 A
-10
-2.0 A
SCLK Pull-down Current SCLK = 5.0 V
RST Pull-down Current RST = 5.0 V
10
30 A
25 10
50 30 A V
PWM Pull-down Current SO High State Output Voltage ISO-high = -1.6 mA SO Low State Output Voltage ISO-low = 1.6 mA Input Capacitance on SCLK, SI, Tri-State SO, RST (14)
SOPWR - 0.2 - -
- V 0.4 20 pF
Notes 13. Upper and lower logic threshold voltage levels apply to SI, CS, SCLK, and PWM. 14. This parameter is guaranteed by design; however, it is not production tested.
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions of 3.1 V SOPWR 5.5 V, 5.0 V VPWR 18 V, -40C TA 125C unless otherwise noted. Where applicable, typical values reflect the parameter's approximate average value with VPWR = 13 V, TA = 25C.
Characteristic POWER OUTPUT TIMING (VPWR) Output Slew Rate RL = 60
(15)
Symbol
Min
Typ
Max
Unit
SR 1.0 tDLY (ON) t DLY(OFF) tDLY (SHORT) t DLY(OPEN) t FREQ 1.0 1.0 100 100 - 2.0 2.0 4.0 - - - 10 10 10 450 450 2.0
V/s
Output Turn ON Delay Time (16) Output Turn OFF Delay Time
(16)
s s s s kHz
Output ON Short Fault Disable Report Delay (17) Output OFF Open Fault Delay Time Output PWM Frequency DIGITAL INTERFACE TIMING (CS, SO, SI, SCLK) (23) Required Low State Duration on VPWR for Reset VPWR 0.2V (18) Falling Edge of CS to Rising Edge of SCLK Required Setup Time Falling Edge of SCLK to Rising Edge of CS Required Setup Time SI to Falling Edge of SCLK Required Setup Time Falling Edge of SCLK to SI Required Hold Time SI, CS, SCLK Signal Rise Time (19) SI, CS, SCLK Signal Fall Time
(19) (17)
t RST - t LEAD 100 t LAG 50 t SI (su) 16 t SI (hold) 20 t R (SI) t F (SI) t SO (EN) t SO (DIS) t VALID - - - - - - 5.0 5.0 - - 25 - - - 50 50 80 - - - - - - - 10
s
ns
ns
ns
ns
ns ns ns ns ns
Time from Falling Edge of CS to SO Low-impedance (20) Time from Rising Edge of CS to SO High-impedance
(21)
Time from Rising Edge of SCLK to SO Data Valid (22) Notes 15. 16. 17. 18. 19. 20. 21. 22. 23.
Output slew rate measured across a 60 resistive load. Output turn ON and OFF delay time measured from 50% rising edge of CS to 80% and 20% of initial voltage. Duration of fault before fault bit is set. Duration between access times must be greater than 450s to read faults. This parameter is guaranteed by design; however, it is not production tested. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. Time required for valid output status data to be available on SO pin. Time required for output states data to be terminated at SO pin. Time required to obtain valid data out from SO following the rise of SCLK with 200pF load. This parameter is guaranteed by design. Production test equipment used 4.16MHz, 5.5/3.1V SPI Interface.
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ELECTRICAL CHARACTERISTICS TIMING DIAGRAM
TIMING DIAGRAM
CS
0.2 VDD
t LEAD 0.7 VDD
t LAG
SCLK
0.2 VDD tSI(su) tSI(hold) MSB IN t VALID 0.7 VDD 0.2 VDD MSB OUT LSB OUT t SO(dis) VTri-State
SI
tSO(en)
0.7 VDD 0.2 VDD
SO
Figure 4. SPI Timing Characteristics
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ELECTRICAL CHARACTERISTICS ELECTRICAL PERFORMANCE CURVES
ELECTRICAL PERFORMANCE CURVES
14 IPWR Current into VPWR Pin (mA) 12 10 8 6 4 2 -40 -25 0 25 50 75 100 125 RDS(ON) ()
VPWR @ 13V
1.4 1.2 1.0 0.8 0.6 0.4
VPWR @ 13V
-40 -25
0
25
50
75
100
125
TA, Ambient Temperature (C) Figure 5. IPWR vs. Temperature
TA, Ambient Temperature (C) Figure 7. RDS(ON) vs. Temperature 1.4 1.2 1.0 RDS(ON) () 0.8 0.6 0.4 0.2
TA = 125C
IPWR Current into VPWR Pin (uA) IPWR Current into VPWR Pin (A)
1.4 14 1.2 12 1.0 10 0.8 8 0.6 6 0.4 4 0.2 2
Sleep State IPWR versus Temperature
VPWR @ 13V
TA = 25C TA = -40C
-40 -25 -40 -25
25 50 75 100 125 25 50 75 100 125 TA, Ambient Temperature (C) TA Ambient Temperature Figure 6. Sleep State IPWR vs. Temperature
0 0
0
5
10
15
20
25
VPWR (V) Figure 8. RDS(ON) vs. VPWR
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FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
FUNCTIONAL DESCRIPTION
The 33996 is designed and developed for automotive and industrial applications. It is a 16 output power switch having 24 bit serial control. The 33996 incorporates SMARTMOS technology having CMOS logic, bipolar / MOS analog circuitry, and independent DMOS power output transistors. Many benefits are realized as a direct result of using this mixed technology. A simplified internal block diagram of the 33996 is shown in Figure 2, page 2.
FUNCTIONAL PIN DESCRIPTION CHIP SELECT (CS)
The system MCU selects the 33996 to be communicated with through the use of the Chip Select (CS) pin. When the CS pin is in a logic low state, data can be transferred from the MCU to the 33996 and vise versa. Clocked-in data from the MCU is transferred from the 33996 Shift register and latched into the power outputs on the rising edge of the CS signal. On the falling edge of the CS signal, output fault status information is transferred from the Power Outputs Status register into the device's SO Shift register. The SO pin output driver is enabled when CS is low, allowing information to be transferred from the 33996 to the MCU. To avoid any spurious data, it is essential the high-to-low transition of the CS signal occur only when SCLK is in a logic low state. status information is transferred from the Power Outputs Status register into the device's SO Shift register. The first eight positive transitions of SCLK will provide Any Fault (bit 23), over-voltage fault (bit 22), followed by six logic [0]s (bits 21 to 16). The next 16 successive positive transitions of SCLK provides fault status for output 15 to output 0. Refer to the LOGIC OPERATION section (below) for more information. The SI / SO shifting of data follows a first-in, firstout protocol, with both input and output words transferring the Most Significant Bit (MSB) first.
OUTPUT DRIVER POWER SUPPLY (SOPWR)
The SOPWR pin is used to supply power to the 33996 SO output driver and Power-ON Reset (POR) circuit. To achieve low standby current on VPWR supply, power must be removed from the SOPWR pin. The 33996 will be in reset with all drivers OFF when SOPWR is below 2.5V. The 33996 does not detect over-voltage on the SOPWR supply pin.
SYSTEM CLOCK (SCLK)
The System Clock (SCLK) pin clocks the Internal Shift registers of the 33996. The Serial Input (SI) pin accepts data into the Input Shift register on the falling edge of the SCLK signal, while the Serial Output (SO) pin shifts data information out of the Shift register on the rising edge of the SCLK signal. False clocking of the Shift register must be avoided, ensuring validity of data. It is essential that the SCLK pin be in a logic low state whenever the CS pin makes any transition. For this reason, it is recommended, though not necessary, that the SCLK pin is commanded to a low logic state as long as the device is not accessed (CS in logic high state). When the CS is in a logic high state, any signal at the SCLK and SI pins is ignored and the SO is tri-stated (high impedance).
OUTPUT/INPUT (OUT0 - OUT15)
These pins are low side output switches controlling the load.
RESET (RST)
The Reset (RST) pin is the active low reset input pin used to turn OFF all outputs, thereby clearing all internal registers.
BATTERY INPUT (VPWR)
The VPWR pin is used as the input power source for the 33996. The voltage on VPWR is monitored for over-voltage protection and shutdown. An over-voltage condition (> 50s) on the VPWR pin will cause the 33996 to shut down all outputs until the over-voltage condition is removed. Upon return to normal input voltage, the outputs will respond as programmed by the over-voltage bit in the Global Shutdown / Retry Control register. The over-voltage threshold on the VPWR pin is specified as 27.5 to 35 V with 1.4V typical hysteresis. Following an over-voltage shutdown of output drivers, the over-voltage Fault and the Any Fault bits in the SO bit stream will be logic [1].
SERIAL INPUT (SI)
The Serial Input (SI) pin is used to enter one of seven serial instructions into the 33996. SI SPI bits are latched into the Input Shift register on each falling edge of SCLK. The Shift register is full after 24 bits of information are entered. The 33996 operates on the command word on the rising edge of CS. To preserve data integrity, exercise care not to transition SI as SCLK transitions from high to low state (see Figure 4, page 8).
SERIAL OUTPUT (SO)
The Serial Output (SO) pin transfers fault status data from the 33996 to the MCU. The SO pin remains tri-state until the CS pin transitions to a logic low state. All faults on the 33996 are reported to the MCU as logic [1]. Conversely, normal operating outputs with nonfaulted loads are reported as logic [0]. On the falling edge of the CS signal, output fault
PWM CONTROL (PWM)
The PWM Control pin is provided to support PWM of any combination of outputs. The LOGIC OPERATION section describes the logic for PWM control.
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FUNCTIONAL DESCRIPTION OPERATIONAL MODES
OPERATIONAL MODES
On each SPI communication, a 24 bit command word is sent to the 33996 and 24 bit fault word is received from the 33996. The Most Significant Bit (MSB) is sent and received first. Command Register Definition: 0 = Output Command Off 1 = Output Command On SO Definition: 0 = No fault 1 = Fault
Table 5. Fault Operation
Serial Output (SO) Pins Reports Over-temperature Over-current Output "ON' Open Load Fault Output "OFF'" Open Load Fault Device Shutdowns Over-voltage Total device shutdown at VPWR = 27.5 V to 35 V. Resumes normal operation with proper voltage. Upon recovery all outputs assume previous state or OFF based on the Overvoltage bit in the Global Shutdown/Retry Control Register. Only the output experiencing an over-temperature fault shuts down. Output may auto-retry or remain off according to the control bits in the Global Shutdown/Retry Control Register. Output will remain in current limit 0.9 A to 2.5 A until thermal limit is reached. When thermal limit is reached, device will enter over-temperature shutdown. Output will operate as programmed in the Global Shutdown/Retry Control Register. Fault flag in SO Response word will be set. Fault reported by Serial Output (SO) pin. SO pin reports short to battery/supply or over-current condition. Not reported. SO pin reports output "OFF'" open load condition.
Over-temperature Over-current
MCU INTERFACE DESCRIPTION
In operation the 33996 functions as a 16-output serial switch serving as a microcontroller (MCU) bus expander and buffer with fault management and fault reporting features. In doing so, the device directly relieves the MCU of the fault management functions. The 33996 directly interfaces to an MCU and operates at system clock serial frequencies up to 6.0MHz using a Serial Peripheral Interface (SPI) for control and diagnostic readout. Figure 9 shows the basic SPI configuration between an MCU and one 33996. MC68HCXX Microcontroller
MOSI Shift Register MISO SCLK Receive Buffer RST Parallel Ports CS PWM To Logic SI SO 24-Bit Shift Register
33996
Figure 9. 33996 SPI Interface with Microcontroller All inputs are compatible with 3.3 / 5.0V CMOS logic levels and incorporate positive logic. An input that is programmed to a logic low state (< 0.8V) will have the corresponding output OFF. Conversely, an input programmed to a logic high state (> 2.2V) will have the output being controlled ON.
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FUNCTIONAL DESCRIPTION OPERATIONAL MODES
Diagnostics is treated in a similar manner -- outputs with a fault will feedback (via SO) to the MCU a logic [1], while normal operating outputs will provide a logic [0]. The 33996 may be controlled and provide diagnostics using a daisy chain configuration or in parallel mode. Figure 10 shows the daisy chain configuration using the 33996. Data from the MCU is clocked daisy chain through each device while the Chip Select bit (CS) is commanded low by the MCU. During each clock cycle, output status from the daisy-chained 33996s is being transferred back to the MCU via the Master In Slave Out (MISO) line. On rising edge of CS, data stored in the input register is transferred to the output driver. Daisy chain control of the 33996 requires 24 bits per device. Multiple 33996 devices can be controlled in a parallel input fashion using the SPI. Figure 11, page 12, illustrates potentially 32 loads being controlled by two dedicated parallel MCU ports used for chip select.
MC68HCXX Microcontroller
MOSI Shift Register MISO SCLK PWM1 PWM2 SI SO SCLK CS PWM RST
33996
Parallel Ports
33996
SI SO SCLK CS PWM RST
Figure 10. 33996 SPI System Daisy Chain
MC68HCXX Microcontroller
MOSI Shift Register MISO SCLK PWM1 Parallel Ports PWM2 RST SI SO
33996
SCLK CS PWM
33996
SI SO SCLK CS PWM RST
Figure 11. Parallel Inputs SPI Control
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Analog Integrated Circuit Device Data Freescale Semiconductor
LOGIC COMMANDS AND REGISTERS INTRODUCTION
LOGIC COMMANDS AND REGISTERS
INTRODUCTION
The 33996 provides flexible control of 16 low-side driver outputs. The device allows PWM and ON /OFF control through the use of several 24 bit input command words. This section describes the logic operation and command registers of the 33996. The 33996 message set consists of seven messages as shown in Table 6. Bits 23 through18 determine the specific Table 6. SPI Control Commands
MSB Bits 22 0 0 21 0 0 20 0 0 19 0 0 18 0 1 17 X X Thermal Bit 0 X X 16 X X Overvoltage 0 X X 15 0 0 14 0 0 13 0 0 12 0 0 11 0 0 10 0 0 9 0 0 8 0 0 7 0 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 LSB 0 0 0
command and bits 15 through 0 determine how a specific output will operate. The 33996 operates on the command word on the rising edge of CS. Note Upon Power-ON Reset all bits are defined as shown in Table 6.
Commands
ON/OFF Control 0 = off, 1 = on Open Load Current Enable 0 = disable, 1 = enable Global Shutdown/Retry Control 0 = shutdown, 1 = retry SFPD Control 1 = therm only, 0 = VDS PWM Enable 0 = SPI only, 1 = PWM AND/OR Control 0 = PWM pin AND with SPI 1 = PWM pin OR with SPI Reset SO Response 0 = No Fault, 1 = Fault
23 0 0
0
0
0
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0 0
0 0
0 0
0 1
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
0 0
0 0
0 0 0
1 1 0
0 1 0
1 0 0
X X 0
X X 0
0 X
0 X
0 X
0 X
0 X
0 X
0 X
0 X
0 X
0 X
0 X
0 X
0 X
0 X
0 X
0 X
Any overvoltFault age
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ON/OFF CONTROL REGISTER
To program the 16 outputs of the 33996 ON or OFF, a 24 bit serial stream of data is entered into the SI pin. The first 8 bits of the control word are used to identify the on/off command and the remaining 16 bits are used to turn ON or OFF the specific output driver.
OPEN LOAD CURRENT ENABLE CONTROL REGISTER
The Open Load Current Enable Control register is provided to enable or disable the 50A open load detect pulldown current. This feature allows the device to be used in LED applications. Power-ON Reset (POR) or the RST pin or the RESET command disables the 50A pull-down current. No open load fault will be reported with the pull-down current disabled. For open load to be active, the user must program the Open Load Current Enable Control register with logic [1].
outputs when returning from over-voltage. Setting the overvoltage bit to logic [0] will force all outputs to remain off when VPWR returns to normal level. Setting the over-voltage bit to logic [1] will command outputs to resume their previous state when VPWR returns to normal level. Bit 17 is the global thermal bit. When bit 17 is set to logic [0], all outputs will shut down when thermal limit is reached and remain off even after cooled. With bit 17 set to logic [1], all outputs will shut down when thermal limit is reached and will retry when cooled.
SHORT FAULT PROTECT DISABLE (SFPD) CONTROL REGISTER
All outputs contain current limit and thermal shutdown with programmable retry. The SFPD control bits are used for fast shutdown of the output when over-current condition is detected but thermal shutdown has not been achieved. The SFPD Control register allows the user to select specific outputs for incandescent lamp loads and specific outputs for inductive loads. By programming the specific SFPD bit as logic [1], output will rely on over-temperature shutdown only. Programming the specific SFPD bit as logic [0] will shut down the output after 100 to 450s during turn on into short circuit. The decision for shutdown is based
GLOBAL SHUTDOWN/RETRY CONTROL REGISTER
The Global Shutdown/Retry Control register allows the user to select the global fault strategy for the outputs. The over-voltage control bit (bit 16) sets the operation of the
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LOGIC COMMANDS AND REGISTERS INTRODUCTION
on output drain-to-source voltage (VDS ) > 2.7V. This feature is designed to provide protection to loads that experience more than expected currents and require fast shutdown. The 33996 is designed to operate in both modes with full device protection.
OR control to occur, the PWM Enable bit must be set to logic [1].
On/Off Control Bit On/Off Control Bit
PWM Enable Bit
To Gate Control
PWM ENABLE REGISTER
The PWM Enable register determines the outputs that are PWM controlled. The first 8 bits of the 24 bit SPI message word are used to identify the PWM enable command, and the remaining 16 bits are used to enable and disable the PWM of the output drivers. A logic [0] in the PWM Enable register will disable the outputs as PWM. A logic [1] in the PWM Enable register will set the specific output as a PWM. Power-ON Reset or the RST pin or the RESET command will set the PWM Enable register to logic [0].
PWM IN AND/OR Control Bit
On/Off control Bit PWM IN
Figure 12. PWM Control Logic Diagram
SERIAL OUTPUT (SO) RESPONSE REGISTER
Fault reporting is accomplished through the SPI interface. All logic [1s] received by the MCU via the SO pin indicate fault. All logic [0s] received by the MCU via the SO pin indicate no fault. All fault bits are cleared on the positive edge of CS. SO bits 15 to 0 represent the fault status of outputs 15 to 0. SO bits 21 to 16 will always return logic [0]. Bit 22 provides over-voltage condition status and bit 23 is set when any fault is present in the IC. The timing between two write words must be greater than 450s to allow adequate time to sense and report the proper fault status.
AND/OR CONTROL REGISTER
The AND /OR Control register describes the condition by which the PWM pin controls the output driver. A logic [0] in the AND /OR Control register will AND the PWM input pin with the ON /OFF Control register bit. Likewise, a logic [1] in the AND /OR Control register will OR the PWM input pin with the ON /OFF Control register bit (see Figure 12). For the AND /
RESET COMMAND
The RESET command turns all outputs OFF and sets the following registers to a POR state (refer to Table 6). * ON/OFF Control Register * SFPD Control Register * PWM Enable Register * AND/OR Control Register The Open Load Current Enable and the Global Shutdown Registers are not affected by the RESET command.
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Analog Integrated Circuit Device Data Freescale Semiconductor
TYPICAL APPLICATIONS INTRODUCTION
TYPICAL APPLICATIONS
Power Consumption The 33996 has been designed with one Sleep mode and one Operational mode. In Sleep mode (SOPWR 2.0V) the current consumed by the VPWR pin is less than 10A. To place the 33996 in Sleep mode, turn all outputs OFF and remove power from the SOPWR pin. During normal operation, 500A is drawn from the SOPWR supply and 8.0mA from the VPWR supply. Paralleling of Outputs Using MOSFETs as output switches allows the connection of any combination of outputs together. The RDS(ON) of MOSFETs has an inherent positive temperature coefficient, providing balanced current sharing between outputs without destructive operation. This mode of operation may be desirable in the event the application requires lower power dissipation or the added capability of switching higher currents. Performance of parallel operation results in a corresponding decrease in RDS(ON), while the Output Current Limit increases correspondingly. Output OFF Open Load Detect current may increase based on how the Output OFF Open Load Detect is programmed. Paralleling outputs from two or more different IC devices is possible but not recommended. Care must be taken when paralleling outputs for inductive loads. The Output Voltage Clamp of the output drivers may not match. One MOSFET output must be capable of the inductive energy from the load turn OFF. SPI Integrity Check Checking the integrity of the SPI communication is recommended upon initial power-up of the SOPWR pin. After initial system start-up or reset, the MCU writes one 48-bit pattern to the 33996. The first 24 bits read by the MCU is the fault status of the outputs, while the second 24 bits is the first bit pattern sent. By the MCU receiving the same bit pattern it sent, bus integrity is confirmed. Please note the second 24 bits the MCU sends to the 33996 are the command bits and will program registers or activate outputs on the rising edge of
CS.
enabled, the 33996 will only shut down the pull-down current in Sleep mode or when disabled via the SPI. During output switching, especially with capacitive loads, a false Output OFF Open Load Fault may be triggered. To prevent this false fault from being reported, an internal fault filter of 100 to 450s is incorporated. The duration for which a false fault may be reported is a function of the load impedance, RDS(ON), COUT of the MOSFET, as well as the supply voltage, VPWR. The rising edge of CS triggers the builtin fault delay timer. The timer must time out before the fault comparator is enabled to detect a faulted threshold. Once the condition causing the Open Load Fault is removed, the device resumes normal operation. The Open Load Fault, however, will be latched in the output SO Response register for the MCU to read. Shorted Load Fault A shorted load (over-current) fault can be caused by any output being shorted directly to supply, or by an output experiencing a current greater than the current limit. Three safety circuits progressively in operation during load short conditions afford system protection: 1. The device's output current is monitored in an analog fashion using a SENSEFET approach and is current limited. 2. With the output in current limit, the drain-to-source voltage will increase. By setting the SFPD bit to 0, the output will shut down on VDS > 2.7V typical after 450s. 3. The device's output thermal limit is sensed and when attained causes only the specific faulted output to shutdown. The device remains OFF until cooled. The device then operates as programmed by the shutdown/ retry bit. The cycle continues until the fault is removed or the command bit instructs the output OFF. All three protection schemes set the Fault Status bit (bit 23 in the SO Response register) to logic [1]. Under-voltage Shutdown An under voltage SOPWR condition results in the global shutdown of all outputs and reset of all control registers. The under-voltage threshold is between 2.0 and 3.0V. An under-voltage condition at the VPWR pin results in an output shutdown and reset. The under-voltage threshold is between 3.2 and 3.5V. When VPWR is between 5.0 and 3.5V, the output may operate per the command word and the status is reported on SO pin, though this is not guaranteed. Output Voltage Clamp Each output of the 33996 incorporates an internal voltage clamp to provide fast turn-OFF and transient protection of each output. Each clamp independently limits the drain-tosource voltage to 50V. The total energy clamped (EJ) can be
33996
Output OFF Open Load Fault An Output OFF Open Load Fault is the detection and reporting of an open load when the corresponding output is disabled (input bit programmed to a logic low state). The Output OFF Open Load Fault is detected by comparing the drain-to-source voltage of the specific MOSFET output to an internally generated reference. Each output has one dedicated comparator for this purpose. Each 33996 output has an internal 50A pull-down current source. The pull-down current is disabled on power-up and must be enabled for Open Load Detect to function. Once
Analog Integrated Circuit Device Data Freescale Semiconductor
15
TYPICAL APPLICATIONS INTRODUCTION
calculated by multiplying the current area under the current curve (IA) times the clamp voltage (VCL) (see Figure 13). Characterization of the output clamps, using a single pulse non-repetitive method at 0.3A, indicates the maximum energy to be 50mJ at 150C junction temperature per output.
Drain-to-Source = 50 V) Voltage (V CL Clamp 45 V) Voltage (VCL = 50V)
Drain-to-Source C lamp
All outputs consist of a power MOSFET with an integral substrate diode. During reverse battery condition, current will flow through the load via the substrate diode. Under this circumstance relays may energize and lamps will turn on. If load reverse battery protection is desired, a diode must be placed in series with the load. Over-temperature Fault Over-temperature detect circuits are specifically incorporated for each individual output. The shutdown following an over temperature condition depends on the control bit set in the Global Shutdown / Retry Control register. Each independent output shuts down at 155C to 180C. When an output shuts down due to an Over-temperature Fault, no other outputs are affected. The MCU recognizes the fault by a logic [1] in the Fault Status bit (bit 23 in the SO Response register). After the 33996 has cooled below the switch point temperature and 10C hysteresis, the output will function as defined by the shutdown / retry bit 17 in the Global Shutdown/Retry Control register.
Drain Voltage Drain Voltage
Drain Current Drain Current (I(ID== 0.3 A) D 0.3A)
Clamp Energy Clamp Energy (EJ = IAVG x V CL) (E = I x V )
J A CL
Drain-to-Source ON Drain-to-Source ON Voltage (V Voltage (VDS(O N)) ) DS(ON)
GND G ND
Curren t Area (IA )
Time Time
Figure 13. Output Voltage Clamping Reverse Battery Protection The 33996 device requires external reverse battery protection on the VPWR pin.
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Analog Integrated Circuit Device Data Freescale Semiconductor
PACKAGING PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
Important: For the most current package revision, visit www.freescale.com and search on keyword for 98A number listed below.
EK SUFFIX (PB-FREE) 32-PIN SOICW EP 98ARL10543D REVISION C
33996
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PACKAGING PACKAGE DIMENSIONS (CONTINUED)
PACKAGE DIMENSIONS (CONTINUED)
EK SUFFIX (PB-FREE) 32-PIN SOICW EP 98ARL10543D REVISION C
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Analog Integrated Circuit Device Data Freescale Semiconductor
PACKAGING PACKAGE DIMENSIONS (CONTINUED)
EK SUFFIX (PB-FREE) 32-PIN SOICW EP 98ARL10543D REVISION C
33996
Analog Integrated Circuit Device Data Freescale Semiconductor
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ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 2.0)
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
Introduction This thermal addendum is provided as a supplement to the MC33996 technical datasheet. The addendum provides thermal performance information that may be critical in the design and development of system applications. All electrical, application, and packaging information is provided in the datasheet. Packaging and Thermal Considerations The MC33996 is offered in a 32 pin SOICW exposed pad, single die package. There is a single heat source (P), a single junction temperature (TJ), and thermal resistance (RJA). TJ
=
33996EK
32-PIN SOICW-EP
RJA
.
P
The stated values are solely for a thermal performance comparison of one package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a package in an application-specific environment. Stated values were obtained by measurement and simulation according to the standards listed below.
EK (PB-FREE) SUFFIX 98ARL10543D 32-PIN SOICW-EP Note For package dimensions, refer to the 33996 data sheet.
Standards Table 7. Thermal Performance Comparisons
Thermal Resistance RJA RJB
(1), (2) (2), (3)
[C/W] 29 9.0 69 2.0
*All Measurements are in Millimeters
1.0 1.0 0.2 0.2
RJA (1), (4) RJC (5)
Notes: 1. Per JEDEC JESD51-2 at natural convection, still air condition. 2. 2s2p thermal test board per JEDEC JESD51-5 and JESD51-7. 3. Per JEDEC JESD51-8, with the board temperature on the center trace near the center lead. 4. Single layer thermal test board per JEDEC JESD51-3 and JESD51-5. 5. Thermal resistance between the die junction and the exposed pad surface; cold plate attached to the package bottom side, remaining surfaces insulated.
32 Pin SOICW-EP 0.65 Pitch 11.0 mm x 7.5mm Body 4.6 mm x 5.7 mm Exposed Pad
Figure 14. Surface Mount for SOICW Exposed Pad
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Analog Integrated Circuit Device Data Freescale Semiconductor
ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 2.0)
A
OUT0 OUT1 SOPWR OUT2 OUT3 VPWR GND GND GND GND SCLK OUT4 OUT5 OUT6 OUT7
CS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OUT15 OUT14 PWM OUT13 OUT12
RST
GND GND GND GND SO OUT11 OUT10 SI OUT9 OUT8
33996 Pin Connections
32-Pin SOICW EP 0.65 mm Pitch 11.0mm x 7.5mm Body 4.6 x 5.7mm exposed pad
Device on Thermal Test Board Material:
Figure 15. Thermal Test Board Table 8. Thermal Resistance Performance
A [mm2] 0 300 600 RJA [C/W] 70 49 47
Single layer printed circuit board FR4, 1.6mm thickness Cu traces, 0.07 mm thickness 80 mm x 100mm board area, including edge connector for thermal testing Cu heat-spreading areas on board surface Natural convection, still air
Outline:
Area A: Ambient Conditions:
RJA is the thermal resistance between die junction and ambient air.
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ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 2.0)
80 Thermal Resistance [C/W] 70 60 50 40 30 20 10 0 0 300 Heat Spreading Area A [mm] 600
x
RJA [C/W]
Figure 16. Device on Thermal Test Board RJA
100 Thermal Resistance [C/W]
10
1
x
RJA [C/W]
0.1 1.00E-03
1.00E-02
1.00E-01
1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04 Time[s]
Figure 17. Transient Thermal Resistance RJA, 1 W Step response, Device on Thermal Test Board Area A = 600 (mm2)
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Analog Integrated Circuit Device Data Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
REVISION 3 4 5
DATE 12/2005 9/2006 4/2007
DESCRIPTION OF CHANGES * * * * * * Implemented Revision History page Changed Static Electrical Table, IPWR (SS) Min characteristics, from "-10" to "-". Added Thermal Addendum Minor labeling corrections to 33996 Simplified Internal Block Diagram on page 2 - changed pins SCLK to CS and CSB to SCLK. Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from MAXIMUM RATINGS on page 4. Added note with instructions from www.freescale.com. Added the EK package type to the included thermal addendum. Added MCZ33996EK/R2. Updated package drawing Added Exposed Pad pin to Pin Definitions (Table 1) on page 3.
6 7 8.0
6/2007 8/2008 8/2008
* * *
33996
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23
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MC33996 Rev. 8.0 8/2008

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